1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming a bottom electrode with an enlarged surface area.
2. Description of the Related Art
Because the integration of integrated circuits is increasing, it is important for the semiconductor industry to consider new manufacturing techniques that enable devices to be fabricated on a sub-micron scale. In a fabrication process for a dynamic random access memory (DRAM), the size of a DRAM capacitor needs to be reduced in order to decrease the planar area occupied by the capacitor. However, size reduction decreases the surface area of a bottom electrode of the DRAM capacitor. Hence, the charge-storage capacity of the capacitor is reduced.
One way to increase charge-storage ability of the DRAM capacitor is to use an HSG-Si layer for forming a bottom electrode. An electrode formed with the HSG-Si layer has a greater surface area, and therefore a greater capacitance for the capacitor is obtained because the HSG-Si layer provides a rough, granular surface.
FIGS. 1A through 1D are schematic, cross-sectional views showing a conventional method of fabricating a bottom electrode with an HSG-Si layer.
In FIG. 1A, a source/drain region 102 of a transistor (not shown) is formed in a substrate 100. A patterned dielectric layer 104 is formed on the substrate 100 to cover the source/drain region 102. The patterned dielectric layer 104 comprises an opening 105 exposing a portion of the source/drain region 102. A polysilicon layer 106 is formed on the dielectric layer 104 to fill the opening 105. The polysilicon layer 106 is electrically coupled with the source/drain region 102. An HSG-Si layer 108 is formed on the polysilicon layer 106.
In FIG. 1B, a patterned photoresist layer 110 is formed over the polysilicon layer 106 to cover the HSG-Si layer 108. The patterned photoresist layer 110 comprises an opening 112 that exposes a portion of the HSG-Si layer 108 on the polysilicon layer 106.
A dry etching step is performed with the patterned photoresist layer 110 serving as a mask. A portion of the HSG-Si layer 108 and the polysilicon layer 106 are removed to form a recess 114 with a vertical sidewall in the polysilicon layer 106. The photoresist layer 110 is removed to form a structure as shown in FIG. 1C.
In FIG. 1D, the polysilicon layer 106 and the HSG-Si layer 108 layer are patterned by a conventional photolithographic and etching process. A bottom electrode 106a with an HSG-layer 108a is formed.
In the above-described steps, the recess 114 with a vertical sidewall is formed in order to increase the surface area of the bottom electrode 106a in a fixed planar area. However, as shown in FIG. 1D, the increase surface area provided by the recess 114 with a vertical sidewall is small. Thus, the increase in bottom electrode 106a capacitance is limited. Moreover, the recess 114 is formed with a vertical sidewall, which causes difficulty during the subsequent ion implantation step. In the ion implantation step, it is difficult to amorphize the vertical sidewall of the recess 114. Thus, it is difficult to form an HSG-Si layer in the recess 114.